Depletion mode SCR for low capacitance ESD input protection

ABSTRACT

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of a heavily doped P+ contact area residing in an N well region on a P substrate and electrically connected to the input pad of active integrated field effect transistor devices. NFET devices with floating gates and drains to reduce capacitance are located in the substrate near the N-well. The NFET source elements as well as the substrate are connected to ground. The NFETs are isolated from the N-well and associate P+ contact area by shallow trench isolation (STI) structures that reduce the NFET drain to substrate and N-well to substrate junction boundary area with a subsequent reduction in the junction capacitance. A voltage pulse from an ESD event will cause the SCR structure and associated parasitic bipolar transistors to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates generally to the structure andmanufacturing process of a FET semiconductor device for ESD protectionof electronic circuit devices and more particularly to a depletion modeSCR for low capacitance input ESD protection particularly suited to highfrequency applications.

[0003] (2) Description of Prior Art

[0004] Because of high input impedance and thin oxide gate structures,the problem of electrostatic discharge damage (ESD) with field effecttransistor (FET) devices can be severe. Therefore the input/output (I/O)circuit locations or pads usually have a protective device connectedbetween the I/O pad and the internal circuits which allows the ESDcurrent to be shunted to ground, protecting the active internal circuitsfrom damage.

[0005] With prior art devices, the capacitance associated with the ESDprotection device on the active circuit input pad can be in the order of0.27 picofarads (pF) or greater. This capacitance is caused to a largedegree by the N-well-P-substrate junction capacitance. For some logicoperation application speeds, this capacitance may be acceptable.However, in high frequency application such as radio frequency (RF) orother applications in the megahertz to gigahertz range, the inputcapacitance should be minimized as much as possible to avoid circuitperformance degradation.

[0006] In the “Prior Art” as shown in FIG. 1, the active circuit signalinput pad 108 is electrically connected to a P+ contact 320 of a N-well180 that resides within a P substrate 100. The input pad is alsoelectrically connected to the N+ drain 241 of NFET1 and N+ drain 242 ofNFET2. NFET1 source 261 and NFET2 source 262 are electrically connectedto a second voltage source, typically ground as shown in FIG. 1. The Psubstrate 100 is also connected to the second voltage, or ground,through the P+ substrate contacts 300. Depicted are the parasiticbipolar PNP transistors T11 and T12, and the parasitic bipolar NPNtransistors T13, T14, T15, T16, and resistors R11, R12, R13, R14 whichexist within the structure. Also shown is diode D11. Parasitic bipolartransistors T11 and T13 effectively function as a PNPN SCR device as doparasitic transistors T12 and T14.

[0007] An ESD incident pulse will propagate through D11 and the basecollector junction of T11 and T12 turning on T13, T14 T15 and T16,shunting the ESD current to ground. The circuit has appropriate feedbackto maintain the shunted current flow until the ESD event is terminated.The device does offer ESD protection, but there is a large capacitanceof approximately 0.27 pF associated with this prior art design. Aspreviously mentioned, the capacitance comes primarily from the N well300 to P substrate 100 junction as well as from the N+ NFET drain 241and the P substrate 100 junction. This level of capacitance on the inputcircuit of an RF device can be detrimental to circuit high frequencyperformance. The invention provides a novel and unique structure andprocess that provides effective ESD protection while reducing the devicecapacitance by a nominal order of magnitude to the range of 0.02 to 0.03pF.

[0008] The following patents and reports pertain to ESD protection.

[0009] U.S. Pat. No. 5,537,284 (Haas, Jr. et al.) ElectrostaticDischarge Protection Device

[0010] U.S. Pat. No. 5,821,572 (Walker et al.) Simple BICMOS Process forCreation of Low Trigger Voltage SCR and Zener Diode Protection

[0011] U.S. Pat. No. 5,825,600 (Watt) Fast Turn-On Silicon ControlledRectifier (SCR) for Electrostatic Discharge (ESD) Protection

[0012] U.S. Pat. No. 6,074,899 (Voldman) 3-D CMOS-ON-Soi ESD structureand Method

[0013] The following technical reports also refer to the subject of ESDprotection in MOS circuits

[0014] Wu et al., “ESD Protection for Output Pad with Well-CoupledField-Oxide Device in 0.5 um CMOS Technology,” IEEE Transactions onElectron Devices, Vol. 44, No. 3, March 1997, IEEE

[0015] Ker et al., “ESD Protection Design on Analog Pin with Very LowInput Capacitance for High-Frequency or Current-Mode Applications,” IEEEJournal of Solid-State Circuits, Vol. 35, No. 8, August 2000, IEEE

[0016] Kleveland et al., “Distributed ESD Protection for High-SpeedIntegrated Circuits,” IEEE Electron Device Letters, Vol. 21, No. 8,August 2000, IEEE

SUMMARY OF THE INVENTION

[0017] Accordingly, it is the primary objective of the invention toprovide an effective and manufacturable method and structure forreducing the capacitance of the protective device providing resistanceto the potential damage caused by the phenomenon known as electrostaticdischarge (ESD) by utilizing a low capacitance depletion mode SCRconnected to an input pad of an integrated circuit device.

[0018] It is further objective of the invention to improve ESDprotection for high frequency and radio frequency (RF) application byproviding a low input capacitance structure that will have minimumimpact on device performance while maintaining reasonable ESD protectionlevels.

[0019] A still additional objective of the invention is to provide theESD protection with reduced capacitance without changing thecharacteristics of the internal circuits being protected and by using aprocess compatible with the process of integrated MOS devicemanufacturing.

[0020] The above objectives are achieved in accordance with the methodsof the invention that describes a structure and a manufacturing processfor semiconductor ESD protection devices with reduced input capacitance.A heavily doped P+ contact area residing in an N well region isconnected to the input pad of active integrated field effect transistors(FETs). N-channel field effect transistor (NFET) N+ drain areas locatedadjacent to and on either side of the N-well within the P substratebody, as are the NFET N+ source regions and P+ substrate contact areas.

[0021] A unique feature of the invention is that it utilizes shallowtrench isolation (STI) elements to reduce the NFET drains to substratejunction capacitance, and the N-well and associated P+ contact junctioncapacitance. This isolation elements are locate between the N-well P+contact region and the NFET N+ drain regions and straddle the N-well tosubstrate junction boundary in the surface region. These STI elementshave the effect of reducing the N+ drain to substrate boundary area, aswell as N well to P substrate boundary area with a subsequent reductionin the input capacitance. In addition, the invention allows the NFETgates and drains to be electrically floating which further reduces thecapacitance on the input pad.

[0022] A voltage pulse from an ESD event will cause the parasiticbipolar transistors that effectively from a SCR device structure totrigger providing a path to ground for the ESD current, therebyprotecting the internal circuits from damage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 shows a device cross-section and equivalent circuit diagramof parasitic transistor elements for a prior art ESD protection device.

[0024]FIG. 2 is a cross section of the invention SCR ESD protectiondevice showing the parasitic elements.

[0025]FIG. 3 is a schematic representation of the electrical elements ofthe invention ESD protection device.

[0026]FIG. 4 is a flow chart of the process for the device protectioncircuit.

[0027]FIGS. 5A through 5F shows various stages of manufacture of theinvention structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028]FIG. 3 depicts the cross section of the low input capacitancedepletion mode SCR with isolate N-channel FET elements. The figure alsodepicts the parasitic bipolar transistors elements within the structure.The structure is formed as indicated by the flow description shown inFIG. 4. A N-well 18 is created within the substrate 10. Multiple shallowtrench isolation (STI) elements 20, are created within the substratesurface region, which abut the P+ N-well contact region 32, and bridgethe N-well 18 to substrate 10. Poly gate elements 25, 27, are created onthe substrate surface. The gate elements have an oxide insulationelement and doped poly conductor element. N+ source regions 61, 62 andN+ drain regions are created which in conjunction with the gateelements, form NFET1 and NFET2. Several P+ contact regions 30 arecreated within the substrate 10 near the NFET source regions 61, 62.Also created is a P+ contact region 32 within the N-well 18. One aspectof the invention is to allow the NFET1 and NFET2 gates 25, 27 and drains41, 42 to be floating electrically to minimize junction capacitance. Afirst electrical conductor system is created to connect the N-well 18 P+contact 32 to a first voltage source, typically the active integratedcircuit signal input pad 8. At the same time a second electricalconductor system is created which connects NFET1 source 61 and NFET2source 62 as well as the substrate P+ contacts 30 to a second voltagesource, typically ground. A passivation layer is created to protect theESD protection device form the environment.

[0029] The vertical parasitic PNP bipolar transistors T1 and T2 depictedin FIG. 2 are formed from the N-well P+ contact region 32 for theemitters, the N-well region 18 for the base elements, and the Psubstrate 10 for the collectors. The diode D1 is formed with the anodebeing the P+ N-well contact region 32 and the cathode being the N-well18. The resistors R1 and R2 are representative of the spreadingresistance in the N-well area 18. Lateral parasitic NPN bipolartransistors T3 and T4 are formed from the N+ FET drains 41, 62 for theemitters, the P substrate 10 for the base regions, and the N-well 18 forthe collectors. R3 and R4 are representative of the resistance in thesubstrate body 10 and are typically in the 200 to 2000 ohms per squarerange.

[0030] A representative electrical schematic of the parasitic bipolartransistors, the NFET elements and the input diode is shown in FIG. 4.When an ESD voltage incidence occurs, the charge through the diode D1turns on the parasitic transistors T1 and T2 that then conduct part ofthe ESD current to ground. The collector currents flowing through R3 andR4 create a forward bias for transistors T3 and T4, turning them onalso. The parasitic bipolar transistors T1 and T3 essentially form a SCRdevice as do transistors T2 and T4. Once triggered, the ESD currentflows until the incident voltage is removed. This multiple parasitictransistor configuration provides additional shunt paths to groundenabling the handling of significant ESD current and affording good ESDprotection to the internal active circuits.

[0031] Referring to FIGS. 5A through 5F, the device is typically formedon a substrate 10 from a silicon wafer of 100 crystal orientation with aP doping, typically with Boron, to a level of about 5E15 atoms per cubiccentimeter (a/cm³). A thin layer of silicon dioxide (SiO₂) pad oxide 12is thermally grown or deposited to a thickness of between 70 and 600angstroms (Å) as a stress relief layer. This is followed by a chemicalvapor deposition (CVD) silicon nitride (SiN) layer 14 between 800 and2000 Å thick ad depicted in FIG. 5A. After suitable patterning withphotoresist 16, a dry anisotropic etch is performed typically by a RIEprocess on the nitride and pad oxide in preparation for the N-well 18implant shown in FIG. 5B. A donor dopent such as phosphorous (P) orarsenic (As) is used with a dosage of between 1E11 and 1E14 a/cm² andimplant energy between 30 and 100 KeV to produce the N-well region 18with a dopent density between 5E15 and 1E18 a/cm³. The N-well istypically has a width of between 0.5 and 6 um and a depth of between 0.5and 6 um.

[0032] An oxide layer is grown or deposited over the device surface, andpatterned in preparation for creating the shallow trench isolation (STI)structures 20 as indicated in FIG. 5C.

[0033] A dry anisotropic etch is performed, again typically by a RIEprocess, to open the trench structures 20 in the substrate on eitherside of the N-well 18. These trench elements are typically between 0.1and 3 um in width and between 0.5 and 4 um in depth. A thin protectiveSiO₂ layer 21 is thermally grown over the walls of the open trenches toa thickness between 50 and 500 Å and then the trenches are filled with adielectric 22, typically SiO₂ to complete the isolation structure.

[0034] As depicted in FIG. 5D, processing continues with patterning andetching to prepare for the gate oxide deposition. A thermal growth ofgate oxide 36, typically to a thickness of between 50 and 300 Å, isplaced on the substrate. The gate oxide 36 is covered by a LPCVDdeposition of polysilicon (poly) 36 which is subsequently donor doped toimprove conductivity. A LPCVD of a mask oxide 38 is placed over the poly36, and photoresist patterning is done to prepare for source/drainimplantation. A dry etch is performed on the surface layers to providean opening to the substrate for the source elements 61 and 62, and drainelements 41 and 42 of the NFETs. A donor implant, typically phosphorous(P), with a dosage between 1E14 and 1E17 a/cm² and with an energy ofbetween 10 and 80 KeV is performed. This produces source and drain N+regions with concentrations between 1E19 and 1E21 a/cm³.

[0035]FIG. 5E depicts the structure prepared for the implanting of thesubstrate contact P+ regions 30 and the N-well P+ region 32. Thepartially completed semiconductor is again patterned with photoresist,and anisotropically etched. An acceptor dopent, typically boron (B), isimplanted with a dosage level of between 1E14 and 1E17 a/cm² and with anenergy of between 10 and 80 KeV. Again, this results in a P+concentration of between 1E19 and 1E21 a/cm³.

[0036] The conductor system 64 for the N-well P+ contact and theconductor system 66 for the N+ NFET source elements 61 and 62 and the P+substrate contact s 30 are created by a blanket evaporation of a metal,typically aluminum or aluminum doped with 1% silicon. After evaporationany unwanted metal is etched typically with a RIE process after beingappropriately patterned. A protective passivation layer 68 is typicallydeposited SiO₂ doped with boron and phosphorous to form borophosphorussilicate glass. The deposition typically takes place with a temperaturebetween 400 and 500° C. The deposition is often followed by adensification anneal at a temperature between 700 and 800° C.

[0037] The novel aspects of the invention are that the STI structures aswell as the floating NFET gates and drains have the effect of reducingthe capacitance on the input node of the active circuits. The uniquestructure has the capability of providing full ESD protection throughthe SCR and associated parasitic bipolar transistors while at the sametime enabling reduced input capacitance critical to high frequencyapplications.

[0038] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is
 1. A low capacitance depletion mode SCR and NFETelement integrated circuit semiconductor device structure withassociated parasitic bipolar transistors on a substrate for the purposeof providing electrostatic voltage discharge protection to the activesemiconductor devices comprising: a first doped region of oppositedopent than said substrate; a second doped region within said firstdoped region of opposite dopent than said second doped region; aplurality of third doped regions within said substrate of oppositedopent than said substrate a gate structure overlaying said substratesurface between a first element and second element of said third dopedregions; a gate structure overlaying said substrate surface between athird element and fourth element of said third doped regions; a firstisolation element between said second element of said third doped regionand a first side of said second doped region; a second isolation elementbetween said third element of said third doped regions and a second sideof said second doped region; a plurality of fourth doped regions withinsaid substrate of similar dopent as said substrate; an electricalconnection system for said second doped region; an electrical connectionsystem for said first and fourth elements of said third doped regionsand for the first and second elements of said fourth doped regions; asurface passivation layer for said ESD protection device.
 2. Thestructure according to claim 1 wherein said substrate consists ofsilicon semiconductor material doped to a concentration between 1E15 and1E16 a/cm³.
 3. The structure according to claim 1 wherein said firstdoped region is doped with a donor element such as As to a concentrationbetween 5E15 to 1E18 a/cm³ and has a width between 0.5 to 6 um and adepth between 0.5 and 6 um to form a N-well.
 4. The structure accordingto claim 1 wherein said second doped region is doped with an acceptorelement such as boron to a concentration between 1E19 and 1E21 a/cm³ toform a N-well P+ contact region.
 5. The structure according to claim 1wherein said plurality of third doped regions are doped with an acceptorelement such as arsenic to a concentration of between 1E19 and 1E21a/cm³.
 6. The structure according to claim 1 wherein said first andfourth elements of said third doped regions form the N+ drain regions ofNFET elements.
 7. The structure according to claim 1 wherein said secondand third elements of said third doped regions form the drain regions ofsaid NFET elements and are electrically floating.
 8. The structureaccording to claim 1 wherein said gate elements are comprised of gateoxide to a thickness between 50 and 300 Å, and polysilicon to athickness between 3000 and 6000 Å.
 9. The structure according to claim 1wherein said polysilicon is doped with a donor element to aconcentration between 1E19 and 1E21 a/cm³.
 10. The structure accordingto claim 1 wherein said isolation elements consist of shallow trenchisolation structures with a width of between 0.1 and 3 um and a depth ofbetween 0.5 and 4 um.
 11. The structure according to claim 1 whereinsaid isolation elements are filled with a first layer of SiO₂ to athickness of between 50 and 500 Å and then filled with a second layer ofSiO₂ to said substrate surface.
 12. The structure according to claim 1wherein said plurality of fourth dope regions are doped with an acceptordopent such as boron to a concentration between 1E19 and 1E21 a/cm³ toform P+ contact elements for said substrate.
 13. The structure accordingto claim 1 wherein said electrical connection system for said seconddoped region consists of aluminum metallurgy or aluminum doped with 1%silicon metallurgy, and is connected to a first voltage sourceconsisting of the input pad of said active semiconductor devices. 14.The structure according to claim 1 wherein said electrical connectionsystem for said first and fourth elements of said third doped regionsand for the first and second elements of said fourth doped regionsconsists of aluminum metallurgy or aluminum doped with 1% siliconmetallurgy, and is connected to a second voltage source or ground. 15.The structure according to claim 1 wherein said surface passivationlayer for said ESD protection device consists of deposited SiO₂ dopedwith boron and phosphorous to form BPSG.
 16. A method of forming a lowinput capacitance depletion mode SCR and isolated N channel FET ESDprotection device on a semiconductor substrate comprising: creating aN-well within said semiconductor substrate; creating multiple STIstructures within said substrate bridging said N-well and said substrateboundary in the surface region; creating gate elements on said substratesurface; creating N+ source and drain areas within said substrate oneither side of said gate elements forming NFET elements; creating a P+contact region within said N-well region and creating P+ contact regionswithin said substrate outside of said N-well region; creating a firstand second electrical conductor system for said ESD protection device;creating passivation for said ESD protection device.
 17. The methodaccording to claim 16 whereby said gate elements are comprised of a thinSiO₂ insulation layer and a polysilicon conductor element.
 18. Themethod according to claim 16 whereby said P+ N-well contact region isconnected to the active circuit signal input pad by said firstelectrical conductor system.
 19. The method according to claim 16whereby said gate elements and said NFET N+ source elements areelectrically floating.
 20. The method according to claim 16 whereby saidNFET N+ source elements and said substrate P+ contact elements areconnected to ground by said second electrical conductor system.
 21. Themethod according to claim 16 whereby said conductor system is comprisedof a metallurgy such as aluminum or aluminum doped with silicon.
 22. Themethod according to claim 16 whereby said passivation is a silicon glasssuch as borophosphorus silicate glass.
 23. A method of fabricating a lowinput capacitance depletion mode SCR and isolated N channel FETsemiconductor device with associated parasitic bipolar transistors toprovide ESD protection on a semiconductor substrate comprising: Growinga first layer on said substrate surface; depositing a second layer onsurface of said first layer; defining with a first patterning element aregion for a first doped region; Etching said first and said secondsurface layers for said first doped region; implanting a dopent to formsaid first doped region; reestablishing said surface layers; definingwith a second patterning element regions for isolation elements; etchingsaid surface layers and said substrate creating open shallow trenchesfor said isolation elements; forming a protective covering on open wallsof said open shallow trenches; filling and capping and planarizing saidshallow trench isolation elements; replacing said first and secondsurface layers with a third surface layer; depositing a conductive layeron said third surface layer; defining with a third patterning elementplurality of regions for a third doped region; implanting said thirdregions with a donor element; patterning with a fourth patterningelement for a plurality of fourth doped regions; implanting said fourthdoped regions with an acceptor dopent; forming a conductor system forsaid protection device; forming a passivation layer for said protectiondevice; completing the processing of said protection device.
 24. Themethod according to claim 23 wherein said substrate is doped with adonor element such as phosphorous to provide a P doping density ofbetween 1E15 and 1 E16 a/cm³.
 25. The method according to claim 23wherein said first surface layer is thermally grown SiO₂ to a thicknessof between 70 and 600 Å.
 26. The method according to claim 23 whereinsaid second surface layer is SiN deposited by LPCVD to a thicknessbetween 800 and 2000 Å.
 27. The method according to claim 23 whereinsaid first doped region is formed with an ion implant of phosphorous (P)with an energy level between 30 and 100 KeV and a dosage level between1E11 and 1E14 a/cm² to produce a N-well region with a concentrationbetween 5E15 and 1E18 a/cm³.
 28. The method according to claim 23wherein said shallow trench isolation elements are anisotropicallyetched by reactive ion etching to a width of between 0.1 and 3 um wideand between 0.5 and 4 um deep.
 29. The method according to claim 23wherein said protective coating on said open walls of said open shallowtrenches consists of thermal deposited SiO₂ to a thickness of between 50and 500 Å.
 30. The method according to claim 23 wherein said shallowtrench elements are filled and capped with thermally grown SiO₂.
 31. Themethod according to claim 23 wherein said filled shallow trenchisolation elements are planarized by chemical mechanical polishing. 32.The method according to claim 23 wherein said third surface layer isthermally deposited SiO₂ for gate insulator to a thickness between 50and 300 Å.
 33. The method according to claim 23 wherein said firstconducting layer is polysilicon provided by low pressure chemical vapordeposition at a temperature between 550 and 700° C. using a silanesource or a gas with hydrogen or nitrogen.
 34. The method according toclaim 23 wherein said third doped regions are doped with phosphorous (P)with an energy level between 10 and 80 KeV and a dosage level between1E14 and 1E17 a/cm² to produce N+ source drain areas with a dopentconcentration of between E19 and 21 a/cm³.
 35. The method according toclaim 23 wherein said fourth doped regions are doped with boron with anenergy level between 10 and 80 KeV and with a dosage level between 1E14and 1E17 a/cm² to produce said substrate P+ contact regions with aconcentration of between E19 and E21 a/cm³.
 36. The method according toclaim 23 wherein said conductor system is made by a blanket evaporationof aluminum doped with 1% silicon, followed by a RIE etched to removeunwanted metal.
 37. The method according to claim 23 wherein saidpassivation layer consists of silicon oxide doped with boron andphosphorous to form borophosphorus silicate glass and is thermallydeposited at a temperature between 40 and 500° C.